1) Field of the Invention
The present invention relates to a clock-signal generation device, a communication device, and a semiconductor device. In particular, the present invention relates to a clock-signal generation device which generates and outputs a clock signal, a communication device which transmits and receives data in synchronization with a clock signal, and a semiconductor device which operates based on a clock signal.
2) Description of the Related Art
FIG. 11 is a diagram illustrating a construction of a conventional serial communication device.
As illustrated in FIG. 11, the conventional serial communication device comprises a CPU (central processing unit) 10, a communication-clock generation unit 11, a CPU interface unit 12, a serial-to-parallel conversion unit 13, a parallel-to-serial conversion unit 14, and a transmission-and-reception unit 15.
The CPU 10 controls respective portions of the serial communication device based on programs and data stored in a storage device (not shown) or the like.
The communication-clock generation unit 11 generates a communication clock signal by dividing the frequency of a reference clock signal.
The CPU interface unit 12 converts a data representation format or the like when an operation of data exchange with the CPU 10 is performed.
The serial-to-parallel conversion unit 13 converts received data (serial data) to parallel data in synchronization with the communication clock signal, where the received data is supplied from the transmission-and-reception unit 15.
The parallel-to-serial conversion unit 14 converts transmission data (parallel data) to serial data in synchronization with the communication clock signal.
FIG. 12 is a diagram illustrating a detailed construction of the communication-clock generation unit 11.
As illustrated in FIG. 12, the communication-clock generation unit 11 comprises a subtraction circuit 20, a selector 21, a decision circuit 22, a counter 23, a register 24, a decision circuit 25, a decoder 26, a flip-flop circuit 27, and a selector 28.
The subtraction circuit 20 decrements the output of the counter 23 by one, and supplies the decremented output to the selector 21.
The selector 21 selects the output of the register 24 when the decision circuit 22 determines that the output of the counter 23 becomes “0,” and the output of the subtraction circuit 20 in the other cases. The output selected by the selector 21 is supplied to the counter 23.
The decision circuit 22 determines whether or not the output of the counter 23 is “0.” When the output of the counter 23 is “0,” the decision circuit 22 makes the selector 21 select the output of the register 24. When the output of the counter 23 is not “0,” the decision circuit 22 makes the selector 21 select the output of the subtraction circuit 20.
The counter 23 is a 4-bit counter constituted by four flip-flop circuits, and holds (latches) 4-bit data output from the selector 21 in synchronization with the reference clock signal.
The register 24 stores data for setting a frequency-division ratio.
The decision circuit 25 determines whether or not the data set in the register 24 is “0,” i.e., whether or not a frequency-division ratio of “1” is designated. When the data set in the register 24 is “0,” the decision circuit 25 makes the selector 28 select the reference clock signal so that the reference clock signal is output as it is. When the data set in the register 24 is not “0,” the decision circuit 25 makes the selector 28 select the output of the flip-flop circuit 27.
The output of the decoder 26 becomes “H” or “L” according to the data output from the counter 23 so that the decoder 26 generates a clock signal having a predetermined duty ratio.
The flip-flop circuit 27 latches and outputs the output of the decoder 26 in synchronization with the reference clock signal.
The selector 28 selects the reference clock signal when it is determined that the data in the register 24 is “0.” In the other cases, the selector 28 selects the output of the flip-flop circuit 27. The reference clock signal or the output of the flip-flop circuit 27 selected by the selector 28 is output as the communication clock signal.
Next, the operations of the above conventional serial communication device are explained.
When the serial communication device illustrated in FIG. 11 is powered on, the CPU 10 stores data designating a frequency-division ratio in the register 24 in the communication-clock generation unit 11 through the CPU interface unit 12. For example, in order to set a frequency-division ratio “4,” data “3” is set in the register 24.
At this time, the counter 23 is in an initial state, and the output of the counter 23 is “0.” Therefore, the register 24 makes the selector 21 select the output of the register 24. Thus, the data “3” stored in the register 24 is read out, and stored in the flip-flop circuits constituting the counter 23.
In the above situation, when the above reference clock signal becomes “H,” the data “3” is read out from the counter 23 in synchronization with the leading edge of the “H” state, and supplied to the decoder 26.
The decoder 26 outputs “H” when the output of the counter 23 is “3” or “2,” and “L” when the output of the counter 23 is “1” or “0.” Since, in the above case, the output of the counter 23 is “3,” the output of the decoder 26 becomes “H” in synchronization with the leading edge of the reference clock signal.
The flip-flop circuit 27 latches the output of the decoder 26 in synchronization with a leading edge of the reference clock signal. In this example, the flip-flop circuit 27 latches “H.”
At this time, the decision circuit 25 makes the selector 28 select the output of the flip-flop circuit 27 since the data set in the register 24 is not “0.” Resultantly, the selector 28 outputs the data (“H”) latched in the flip-flop circuit 27.
The data output from the counter 23 is also supplied to the subtraction circuit 20, which decrements the data by one, and supplies the decremented data to the counter 23 through the selector 21. Since, in this case, the data output from the counter 23 is “3,” the subtraction circuit 20 outputs “2,” which is again stored in the counter 23, and output in synchronization with a leading edge of the reference clock signal.
The output of the counter 23 is input into the decoder 26. Since, in this example, the output of the counter 23 is “2,” the output of the decoder 26 becomes “H.” Therefore, the selector 28 still outputs “H.”
Subsequently, when the subtraction circuit 20 outputs the data “1,” this data is supplied through the counter 23 to the decoder 26 as in the above cases. Since the output of the counter 23 is “1,” the output of the decoder 26 is changed to “L.” Consequently, the selector 28 outputs “L.”
Thereafter, when the subtraction circuit 20 outputs “0,” the decoder 26 outputs “L.” Therefore, the output of the selector 28 remains “H.”
At this time, the decision circuit 22 determines that the output of the counter 23 becomes “0,” and makes the selector 21 select the output of the register 24. Resultantly, the data “3” is again read into the counter 23 in synchronization with the next leading edge of the reference clock signal.
By repeating the above operations, it is possible to divide the frequency of the reference clock signal by a predetermined value, and generate a communication clock signal.
The communication clock signal generated as above is supplied to the serial-to-parallel conversion unit 13, the parallel-to-serial conversion unit 14, and the transmission-and-reception unit 15.
When the serial-to-parallel conversion unit 13, the parallel-to-serial conversion unit 14, and the transmission-and-reception unit 15 transmit and receive data, a predetermined number of pulses of the communication clock signal correspond to each bit of serial data. (Hereinafter, pulses of the communication clock signal are referred to as cycles.) For example, in the case where eight cycles correspond to one bit, each bit of serial data is transmitted or received while eight cycles of the communication clock signal are supplied.
The number of bits which can be transmitted and received in a unit time is generally called bit rate. When the period of the reference clock signal is denoted by M, and the frequency-division ratio is N, the period of the communication clock signal is M×N, and the period of each bit is M×N×8. At this time, the bit rate is 1/(M×N×8).
When the frequency of the reference clock signal is 4 MHz (=250 ns), and the frequency-division ratio is four, the number of bits which can be transmitted in a second is 125,000, and the bit rate is 125,000 bps.
FIG. 13 is a diagram indicating relationships between a reference clock signal, a communication clock signal, and transmission data in the case where the frequency-division ratio is four, and eight cycles correspond to one bit. In this example, one cycle of the communication clock signal indicated in FIG. 13, (B) is generated from every four cycles of the reference clock signal indicated in FIG. 13, (A), and every eight cycles of the communication clock signal corresponds to one bit as indicated in FIG. 13, (C).
Incidentally, in order to change the bit rate in the above conventional example, generally, the frequency-division ratio of the reference clock signal is changed. Although the operations in the case where the frequency-division ratio is set to four are indicated in FIG. 13, the operations become as indicated in FIG. 14 in the case where the frequency-division ratio is three. That is, one cycle of the communication clock signal indicated in FIG. 14, (B) is generated from every three cycles of the reference clock signal indicated in FIG. 14, (A), and every eight cycles of the communication clock signal corresponds to one bit as indicated in FIG. 14, (C).
In addition, FIG. 15 is a diagram indicating relationships in the case where the frequency-division ratio is set to five. In this example, one cycle of the communication clock signal indicated in FIG. 15, (B) is generated from every five cycles of the reference clock signal indicated in FIG. 15, (A), and every eight cycles of the communication clock signal corresponds to one bit as indicated in FIG. 15, (C).
The bit rate in the case where the frequency-division ratio is three is 1/(250 ns×3×8)=166,666 bps. On the other hand, the bit rate in the case where the frequency-division ratio is five is 1/(250 ns×5×8)=100,000 bps. In either case, the difference from the 125,000 bps is great.
As explained above, according to the method of controlling the bit rate by changing the frequency-division ratio, the bit rate cannot be changed by a small amount. For example, in order to obtain the bit rate of 120,000 bps, it is necessary to change the period of the reference clock signal per se.
However, if the period of the reference clock signal per se is changed for changing the bit rate, a malfunction can occur in the blocks other than the transmission-and-reception unit 15 since the reference clock signal is also supplied to the blocks other than the transmission-and-reception unit 15.